DocumentCode
2349334
Title
AVF Analysis Acceleration via Hierarchical Fault Pruning
Author
Maniatakos, Michail ; Tirumurti, Chandra ; Jas, Abhijit ; Makris, Yiorgos
Author_Institution
EE Dept., Yale Univ., New Haven, CT, USA
fYear
2011
fDate
23-27 May 2011
Firstpage
87
Lastpage
92
Abstract
The notion of Architectural Vulnerability Factor (AVF) has been extensively used by designers to evaluate various aspects of design robustness. While AVF is a very accurate way of assessing element resiliency, its calculation requires rigorous and extremely time-consuming experiments. In response, designers have introduced various methodologies that allow AVF calculation within reasonable time, at the cost of some loss of accuracy. In this paper, we present a method for calculating the AVF of design elements-using Statistical Fault Injection (SFI)-with equal accuracy but several orders of magnitude faster than traditional SFI techniques. Our method partitions the design into various hierarchical levels and systematically performs incremental fault injections to generate the AVF numbers. The presented method has been applied on an Intel microprocessor, where experimental results corroborate its ability to achieve great speed-up while maintaining perfect accuracy in calculating AVF.
Keywords
computer architecture; fault tolerant computing; microprocessor chips; statistical analysis; systems analysis; AVF analysis; Intel microprocessor; SFI techniques; architectural vulnerability factor; hierarchical fault pruning; incremental fault injections; statistical fault injection; Accuracy; Algorithm design and analysis; Analytical models; Latches; Logic gates; Microprocessors; Out of order;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium (ETS), 2011 16th IEEE European
Conference_Location
Trondheim
ISSN
1530-1877
Print_ISBN
978-1-4577-0483-3
Electronic_ISBN
1530-1877
Type
conf
DOI
10.1109/ETS.2011.42
Filename
5957928
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