Author :
Cherman, V. ; Van der Plas, G. ; De Vos, J. ; Ivankovic, A. ; Lofrano, M. ; Simons, V. ; Gonzalez, M. ; Vanstreels, K. ; Wang, Tao ; Daily, R. ; Guo, Wenyong ; Beyer, G. ; La Manna, A. ; De Wolf, Ingrid ; Beyne, Eric
Abstract :
In this work the effects of 3D stacking technology on the performance of devices are systematically studied. For this study a special chip consisting of a number of stress sensors and vertical interconnect loops was designed and manufactured in 65 nm technology. Local variations of stress with a magnitude of up to 300 MPa are detected at different locations along the chip and are being characterized using finite element modeling and micro-Raman spectroscopy measurements.
Keywords :
Raman spectra; finite element analysis; integrated circuit interconnections; microprocessor chips; stacking; 3D stacking technology; finite element modeling; mechanical stress effects; microRaman spectroscopy measurements; size 65 nm; special chip; stress sensors; vertical interconnect loops; Arrays; Current measurement; Stress; Stress measurement; Temperature sensors; Three-dimensional displays;
