Prediction of harmonic tuning performance in pHEMTs

This paper focuses on the characterization and optimization of microwave power transistors using a commercial on-wafer harmonic load pull system. Specific attention is paid to the output tuning of the second harmonic impedance presented to the device. The ability to quantify the level of accuracy in a load pull system is explored by using various calibration validation methods. Experiments and simulation comparisons are described for a GaAs pHEMT and a GaAs HJFET. The measured harmonic load pull data pointed to different guidance on how one would match the 2^nd harmonic for best performance.