Title :
A digital systolic neural network chip (DSNC)
Author :
Weinberg, N. ; Ginosar, R.
Author_Institution :
Dept. of Electr. Eng., Technion-Israel Inst. of Technol., Haifa, Israel
Abstract :
The DSNC chip implements one neural network layer having 25 fully inter-connected neurons. It is a digital, systolic, pipelined, integer based architecture. The chip is primarily designed for image processing tasks devised upon the basic backpropagation neural-network algorithm. Forward processing as well as learning are supported and carried out in parallel with each other. A network built using this chip can have unlimited number of layers when working in forward mode, and up to three layers if learning is required. The topology of a network is user defined. A chip can handle up to 25 inputs in each input example. Input and output data are nine bits; weights, biases and their updated values are eight bits. A chip can process images of up to 550/spl times/550 pixels in real-time when processing neighborhoods of 25 pixels, and larger images when using smaller neighborhoods. The chip requires about two million transistors and 180 I/O pins.
Keywords :
backpropagation; image processing equipment; neural chips; pipeline processing; real-time systems; systolic arrays; 302500 pixel; 550 pixel; DSNC chip; backpropagation neural-network algorithm; biases; digital systolic neural network chip; forward processing; fully inter-connected neurons; image processing tasks; neural network layer; pipelined integer based architecture; real-time processing; user defined topology; weights; Algorithm design and analysis; Arithmetic; Backpropagation algorithms; Cities and towns; Image processing; Network topology; Neural networks; Neurons; Pixel; Process design;
Conference_Titel :
Electrical and Electronics Engineers in Israel, 1995., Eighteenth Convention of
Conference_Location :
Tel Aviv, Israel
Print_ISBN :
0-7803-2498-6
DOI :
10.1109/EEIS.1995.514159