DocumentCode
235032
Title
Power supply filter for PLL circuit in digital systems
Author
Nam Pham ; Pakbaz, Faraydon ; Zhenrong Jin ; Walls, L.
Author_Institution
IBM Corp., Austin, TX, USA
fYear
2014
fDate
27-30 May 2014
Firstpage
535
Lastpage
540
Abstract
This paper presents an effective design approach for the power supply filter of a phase lock loop (PLL) based clock generator in a multi-core ASIC. The noise sensitivity of different types, filter design, system design issues, and measurement techniques for verification and understanding of jitter behavior on power supply noise are discussed.
Keywords
application specific integrated circuits; digital phase locked loops; digital systems; integrated circuit noise; jitter; noise measurement; power filters; power supply circuits; PLL circuit; application specific integrated circuits; clock generator; digital systems; filter design; jitter behavior understanding; jitter behavior verification; measurement techniques; multicore ASIC; noise sensitivity; phase lock loop; power supply filter; power supply noise; system design issues; Clocks; Jitter; Noise; Noise measurement; Phase locked loops; Power supplies; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th
Conference_Location
Orlando, FL
Type
conf
DOI
10.1109/ECTC.2014.6897336
Filename
6897336
Link To Document