DocumentCode
235035
Title
Coaxial through-package-vias (TPVs) for enhancing power integrity in 3D double-side glass interposers
Author
Kumar, Girish ; Raj, P. Markondeya ; Jounghyun Cho ; Gandhi, Saumya ; Chakraborti, Parthasarathi ; Sundaram, Venky ; Joungho Kim ; Tummala, Rao
Author_Institution
3D Syst. Packaging Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA
fYear
2014
fDate
27-30 May 2014
Firstpage
541
Lastpage
547
Abstract
Double-sided 3D glass interposers and packages, with through package vias (TPV) at the same pitch as TSVs in Si, have been proposed to achieve high bandwidth between logic and memory with benefits in cost, process complexity, testability and thermal over 3D IC stacks with TSV. However, such a 3D interposer introduces power distribution network (PDN) challenges due to increased power delivery path length and plane resonances. This paper investigates the use of coaxial through-package-vias (TPVs) with high dielectric constant liners as an effective method to deliver clean power within a 3D glass package, and provides design and fabrication guidelines to achieve the PDN target impedance. The Coaxial TPV structure is simulated using electromagnetic (EM) solvers and a simplified equivalent circuit model to study via impedance and parasitics. Test vehicles with anodized tantalum oxide capacitors were fabricated in ultra-thin, 100μm thick glass interposers to demonstrate process feasibility, with a capacitance density of 5 nF/mm2. Self-impedance (Z11) of a 3D glass interposer containing the coaxial TPVs was analyzed with variations in (a) Via location, (b) Number of coaxial vias, and (c) Via capacitance and stack-up, to provide optimal PDN design guidelines. Based on the above parameters, the added decoupling vias achieved more than 30% impedance suppression over multiple resonance frequencies between 0.5-6 GHz, providing an effective and flexible PDN design method for double-side 3D glass interposers.
Keywords
anodisation; elemental semiconductors; equivalent circuits; integrated circuit interconnections; integrated circuit packaging; silicon; tantalum compounds; three-dimensional integrated circuits; 3D double-side glass interposers; 3D glass package; PDN target impedance; Si; TPV; TSV; anodized capacitors; coaxial through-package-vias; decoupling vias; equivalent circuit model; frequency 0.5 GHz to 6 GHz; optimal PDN design guidelines; power delivery path length; power distribution network; power integrity; process complexity; size 100 mum; through silicon vias; Capacitance; Capacitors; Films; Glass; Impedance; Three-dimensional displays;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th
Conference_Location
Orlando, FL
Type
conf
DOI
10.1109/ECTC.2014.6897337
Filename
6897337
Link To Document