DocumentCode
235064
Title
Development of process and design criteria for stress management in through silicon vias
Author
Holck, O. ; Nuss, M. ; Grams, A. ; Prewitz, T. ; John, P. ; Fiedler, C. ; Bottcher, M. ; Walter, Hans ; Wolf, M.J. ; Wittler, Olaf ; Lang, K.-D.
Author_Institution
Fraunhofer Inst. for Reliability & Microintegration (IZM), Berlin, Germany
fYear
2014
fDate
27-30 May 2014
Firstpage
625
Lastpage
630
Abstract
In this paper we report experimental results of through silicon vias (TSVs) at an early processing step which are used in a context of reliability assessment. Parameter studies and evaluation of stresses using finite element analysis contribute to an optimization of processing parameters. Our results comprise nanoindentations to characterize copper protrusion, elasticity and hardness from the top as well as on cross-sections into the depth of the TSVs, EBSD analysis of cross-sections to characterize grain size and orientation and seed-layer influence. FIB-images were used to identify failure modes and finite element studies show reasonable agreement to detected stresses and reliability hot spots. Detailed Raman maps are presented as an outlook for further investagtion of stress fields at TSV cross sections. Design criteria to improve the production process are discussed based on the obtained results.
Keywords
integrated circuit design; integrated circuit reliability; three-dimensional integrated circuits; design criteria; finite element analysis; grain orientation; grain size; process development; processing parameter optimization; reliability assessment; seed layer influence; stress management; through silicon vias; Annealing; Copper; Reliability; Silicon; Stress; Through-silicon vias;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th
Conference_Location
Orlando, FL
Type
conf
DOI
10.1109/ECTC.2014.6897351
Filename
6897351
Link To Document