DocumentCode :
2351173
Title :
A chip-level electrostatic discharge simulation strategy
Author :
Qian, Haifeng ; Kozhaya, Joseph N. ; Nassif, Sani R. ; Sapatnekar, Sachin S.
Author_Institution :
Minnesota Univ., Minneapolis, MN, USA
fYear :
2004
fDate :
7-11 Nov. 2004
Firstpage :
315
Lastpage :
318
Abstract :
This work presents a chip-level charged device model (CDM) electrostatic discharge (ESD) simulation method. The chip-level simulation is formulated as a DC analysis problem. A network reduction algorithm based on random walks is proposed for rapid analysis, and to support incremental design. A benchmark with a 2.3M-node VDD net and 1000 I/O pads is checked in 13 minutes, and 10 re-simulations for incremental changes take a total of 9 minutes.
Keywords :
circuit simulation; electrostatic discharge; DC analysis problem; chip-level charged device model; chip-level simulation; electrostatic discharge simulation; network reduction algorithm; Algorithm design and analysis; Analytical models; Biological system modeling; Circuit simulation; Clamps; Computational modeling; Electrostatic discharge; Humans; Protection; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on
ISSN :
1092-3152
Print_ISBN :
0-7803-8702-3
Type :
conf
DOI :
10.1109/ICCAD.2004.1382593
Filename :
1382593
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2351173
بازگشت