Bump geometric deviation on the reliability of BOR WLCSP

To solve the mystery of early thermal cycling failures on a relatively small size (1.6 mm × 2.4 mm) wafer level chip scale package (WLCSP) with bump on re-passivation (BOR) structure, details of bump geometry parameters are looked into. While the under bump metal layer stack is first confirmed within specifications, UBM offset from center point is found greater than typical on the failed units. To fully understand the impact of this bump parameter shift that is defined by lithographic process, additional geometric configurations of the bump structure and materials, as well as bump parameter deviations are studied on the stress in solder, UBM and on chip SiN passivations. The study takes into consideration the thickness/size of UBM, aluminum metal pad, SiN passivation layer and PI re-passivation layer. UBM materials, such as nickel vs copper, are also included in the study. Board-level thermal cycling test (TMCL) is conducted on a WLCSP with 8×8 bump array at 0.4mm pitch. Simulation reveals that size ratio and bump offset indeed change the stress level in the critical passivation layer, and the results well explain the early failures recorded in a device qualification reliability test and follow up experimental verifications. Conclusion of this work should be applied when defining design rules for robust reliability performance and manufacturability of this traditional WLCSP bumping technology.