Versatile thin wafer stacking technology for monolithic integration of temporary bonded thin wafers

This paper will focus on recent results for wafer stacking of temporary bonded wafers for the integration in a monolithic device process. For ease of process integration, this process enables the face-to-back stacking of several device layers. Plasma activated fusion bonding could be shown to be an enabling step to lower annealing temperatures into a CMOS compatible range. Furthermore, plasma activation enables to use thermoplastic adhesives. Two types of test vehicles have been fabricated, showing on the one hand a successful stacking of a 11μm thin device wafer onto another thick substrate wafers. On the other hand, a triple stack of thick substrate wafer and two 20μm thin devices is shown as well. Bonding results have been measured using state-of-the-art measurement techniques, such as infrared scanning, scanning acoustic microscopy and scanning white light interferometry, to detect interface defects, bond integrity and temporary adhesive properties, respectively.