DocumentCode
235220
Title
Effect of high temperature storage on the stress and reliability of 3D stacked chip
Author
Tengfei Jiang ; Chenglin Wu ; Peng Su ; Chia, Pierre ; Li Li ; Ho-Young Son ; Min-Suk Suh ; Nam-Seog Kim ; Im, Jay ; Rui Huang ; Ho, Paul S.
Author_Institution
Microelectron. Res. Center, Univ. of Texas, Austin, TX, USA
fYear
2014
fDate
27-30 May 2014
Firstpage
1122
Lastpage
1127
Abstract
In this work, the effect of high temperature storage (HTS) on the stress in and around Cu TSVs in 3D stacked chips is studied by scanning white beam x-ray microdiffraction. The x-ray microdiffraction measurements were conducted on different die levels in the stacked chips before and after HTS test. High resolution mappings of stress distribution were obtained and compared between pre-HTS and post-HTS for both the Cu via and the surrounding Si. The x-ray microdiffraction technique provides a means for nondestructive, direct stress measurement in a 3D die stack structure. Finite element analysis (FEA) was carried out for the test structure to interpret the measurement results and to discuss the thermal aging effect on the 3D chip. Overall, the results show reduced stress in both Cu and Si after HTS, which can be explained by stress relaxation occurred during HTS. The implication of the HTS results on long term reliability of 3D die stacks is discussed.
Keywords
X-ray diffraction; copper; finite element analysis; integrated circuit reliability; storage; stress effects; three-dimensional integrated circuits; 3D stacked chip reliability; 3D stacked chip stress; Cu; TSV chip; finite element analysis; high temperature storage; scanning white beam X-ray microdiffraction; High-temperature superconductors; Silicon; Strain; Stress; Three-dimensional displays; Through-silicon vias; Tin;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th
Conference_Location
Orlando, FL
Type
conf
DOI
10.1109/ECTC.2014.6897430
Filename
6897430
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