Title :
1.5 GHz robust SRAM array employing dynamic power management scheme
Author :
Kharouf, S. ; Chatila, L. ; Mansour, M. ; Chehab, A.
Author_Institution :
Dept. of Electr. & Comput. Eng., American Univ. of Beirut, Beirut, Lebanon
Abstract :
A low power SRAM macro is customized in 90nm TSMC model technology. The design minimizes the area of the bitcells to achieve a total area of 0.370 mm2. A dynamic supply voltage management scheme is used to reduce the leakage power in the standby mode. The 64 kbits sub-array operates at 1.54 GHz for 1.0V supply voltage. Monte carlo simulation results show that the macro has a 6% failure probability under Vt process variations.
Keywords :
Monte Carlo methods; SRAM chips; low-power electronics; Monte Carlo simulation; SRAM array; TSMC model technology; dynamic power management scheme; dynamic supply voltage management; frequency 1.5 GHz; frequency 1.54 GHz; leakage power; low power SRAM macro; size 90 nm; voltage 1.0 V;
Conference_Titel :
Energy Aware Computing (ICEAC), 2010 International Conference on
Conference_Location :
Cairo
Print_ISBN :
978-1-4244-8273-3
DOI :
10.1109/ICEAC.2010.5702275
