DocumentCode :
2352996
Title :
A new signaling technique for a low power on-chip SerDes transceivers
Author :
Hussein, Ezz Ei-din ; Safwat, Sally ; Ghoneima, Maged ; Ismail, Yehea
fYear :
2010
fDate :
16-18 Dec. 2010
Firstpage :
1
Lastpage :
2
Abstract :
This paper represents a new self timed signaling technique for low power SerDes transceiver. A three level coding technique enables extracting the clock from the data using simple phase detector rather than using complex power hungry blocks such as Clock Data Recovery (CDR) or a Phase Locked Loop (PLL). This SerDes transceiver was implemented using 90nm TSMC technology. The transmitter serializes 8 parallel bits at 1.125GHz, and multiplexes the 10Gbps serial data stream with a 20GHz clock on a single line using three level signaling. The total power consumed in the Tx/Rx pair with the transmission line is 15 mWatt, which is very small as compared to other conventional architectures.
Keywords :
clocks; phase detectors; signalling; transceivers; transmission lines; TSMC technology; bit rate 10 Gbit/s; clock extraction; frequency 1.125 GHz; frequency 20 GHz; low power on-chip serialization and deserialization transceiver; phase detector; power 15 mW; self timed signaling technique; size 90 nm; three level coding technique; transmission line;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Energy Aware Computing (ICEAC), 2010 International Conference on
Conference_Location :
Cairo
Print_ISBN :
978-1-4244-8273-3
Type :
conf
DOI :
10.1109/ICEAC.2010.5702283
Filename :
5702283
Link To Document :
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