Implications of gate stack scaling in sub-100 nm CMOS speed and reliability

Author

Yeap, G.C.-F. ; Krishnan, S. ; Yu, B. ; Xiang, Q. ; Lin, M.-R.

Author_Institution

Adv. Micro Devices Inc., Sunnyvale, CA, USA

fYear

1998

fDate

22-24 June 1998

Firstpage

16

Lastpage

17

Abstract

Scaling of CMOS devices is projected to continue down to the deep sub-100 nm regime. The gate stack (dielectrics-silicon interface, gate dielectrics and gate contact) is arguably the most critical part of the MOSFET. It is widely believed that oxide will be replaced by high K dielectrics when dielectric thickness is 1.5 nm or below due to excessive direct tunneling (DT) gate leakage. In this work, the effects of high K dielectrics and their interactions with poly depletion (PD), mobility, gate DT leakage and channel charge in sub-100 nm CMOS performance and reliability were investigated.

Keywords

CMOS integrated circuits; carrier mobility; dielectric thin films; integrated circuit design; integrated circuit modelling; leakage currents; nanotechnology; permittivity; tunnelling; 100 nm; CMOS device scaling; CMOS performance; CMOS reliability; CMOS speed; MOSFET; Si; SiO/sub 2/-Si; carrier mobility; channel charge; dielectric thickness; dielectrics-silicon interface; direct tunneling gate leakage; gate DT leakage; gate contact; gate dielectrics; gate stack; gate stack scaling; high K dielectrics; oxide replacement; poly depletion; Gate leakage; High K dielectric materials; High-K gate dielectrics; MOSFET circuits; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Device Research Conference Digest, 1998. 56th Annual

Conference_Location

Charlottesville, VA, USA

Print_ISBN

0-7803-4995-4

Type

conf

DOI

10.1109/DRC.1998.731102

Filename

731102