A novel CMOS compatible multi-level flash EEPROM for embedded applications

The development of embedded nonvolatile memory (NVM) is becoming increasingly important for low power mobile systems, and in particular for mobile communications. The aim of this work is to develop a novel flash memory with low additional mask count suitable for embedded applications using an extremely novel approach. The pseudo-floating gate flash EEPROM (PSI) cell is similar to a conventional MOSFET, with polysilicon fillets flanking the gate instead of oxide spacers. This concept was first presented as a single bit cell in 1997 at the NVSM workshop (Papadas et al., IEEE Electron. Dev. Lett., 1997). That work has been extended here to multi-bit storage capability and evaluated using numerical device simulation. The memory action is achieved by modifying the drain series resistance of the transistor by putting charge on the floating polysilicon fillets. Also, since the maximum threshold voltage and transconductance are determined by the intrinsic properties of the MOSFET, the cell does not suffer from over-programming like other cell architectures that address this market. The PSI cell multi-level flash concept has been effectively demonstrated using mixed mode simulation in 0.23 μm CMOS technology and analysis of simulation results shows a possibility of scaling with CMOS in future generations, which is promising for future low power mobile applications.