A PoP structure to support I/O over 2000

The rapid growth of smartphones and tablets in mobile market demands the packaging technology to be in a thinner profile with small form factor and reduce power consumption. The PoP structure is widely used in the package of smart phones to connect memory and Application Processor. Even if TSV is the preferred structure for connecting memory and AP, the high cost of TSV process prohibit TSV for wide presence in the smart phone applications. Recently, I/Os of memory are required to increase from a few hundreds to more than 1000. For wide I/O2, I/Os more than 2000 may be required. We have demonstrated PoP connections over 1000 with pitch of 200 um in last year´s ECTC conference with Unimicron HCP (High Copper Pillar) technology [1]. In preparation to meet future memory requirement and to evaluate the extendibility of Unimicron proposed HCP structure, a test vehicle has been built. The test vehicle consists of a PoP structure with a fine pitch of 100 μm that can support 2472 I/Os in 6 rows around the peripheral area of the die. The package size is in a 12×12 mm² CSP format. The target copper pillar height is 80 μm. The copper pillars with a designed diameter of 70 μm and space of 30 μm. The uniformity of copper pillar height is required to assure the reliable interconnections between the top memory die and the bottom AP. For a designed copper pillar height of 80 μm, tolerance of +/-15 μm is required. In this paper, a method to achieve the copper height uniformity of +/- 15 μm with 100 μm PoP pitch connection will be demonstrated.