DocumentCode :
2353748
Title :
Automatic parallelization of a Petri net-based design representation for high-level synthesis
Author :
Grun, Peter ; Eles, Petru ; Kuchcinski, Krzysztof ; Peng, Zebo
fYear :
1996
fDate :
2-5 Sep 1996
Firstpage :
185
Lastpage :
192
Abstract :
This paper presents an approach to automatic parallelization of an internal design representation for high-level synthesis of hardware structures. It concentrates on aspects which are specific to the parallelization of the Petri net based representation used by our design environment. Preservation of safeness and conflict freeness of the internal representation during parallelization are basic requirements for the correctness of the resulted hardware. A hierarchical Petri net structure has been used as an intermediate representation during parallelization, which results in an important reduction of the complexity of the parallelization process. Experimental results demonstrate the efficiency our approach in the context of the CAMAD high-level synthesis system
Keywords :
CAD; Petri nets; computational complexity; formal specification; hardware description languages; high level synthesis; CAMAD; Petri net-based design representation; automatic parallelization; complexity; conflict freeness; design environment; hardware structures; hierarchical Petri net structure; high-level synthesis; internal design representation; parallelization process; safeness; Circuit synthesis; Computer science; Concurrent computing; Design automation; Design engineering; Digital systems; Hardware; High level synthesis; Information science; Parallel processing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
EUROMICRO 96. Beyond 2000: Hardware and Software Design Strategies., Proceedings of the 22nd EUROMICRO Conference
Conference_Location :
Prague
ISSN :
1089-6503
Print_ISBN :
0-8186-7487-3
Type :
conf
DOI :
10.1109/EURMIC.1996.546381
Filename :
546381
Link To Document :
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