Improved PCB via pattern to reduce crosstalk at package BGA region for high speed serial interface

Crosstalk is one of the root causes to violate jitter compliance in high speed serial link, as the data rate increase and signal density goes up. To minimize cancellation or crosstalk impact, many techniques have been investigated. However, unlike horizontal crosstalk, crosstalk at vertical interconnection has limitation to eliminate. In particular, coupling occurs at the interface of chip and PCB is one of the unavoidable sources of crosstalk. Among three coupling types, TX to TX, RX to RX and TX to RX, TX to RX coupling is detrimental compared to others since the aggressor TX swing is large with high slew rate and the victim RX signal has low swing and slow edge. RX jitter performance is more sensitive to noise coupling. Therefore, it is important to investigate crosstalk impact on RX performance on the system level including IOs, package and PCB. In this paper, the impact of transmitter to receiver crosstalk induced at package balls and PCB vias is characterized. Critical factors causing this near-end crosstalk are identified and analyzed. Additionally, the PCB via pattern is proposed to minimize field interference between TX and RX as simply rotating TX via pair perpendicularly to RX via pair. It is demonstrated that the proposed structure reduces crosstalk significantly.