DocumentCode :
2356939
Title :
Code optimization method utilizing memory addressing operation and its application to DSP compiler
Author :
Iimuro, Satoshi ; Sugino, Nobuhiko ; Nishihara, Akinori ; Fujii, Nobuo
Author_Institution :
Dept. of Phys. Electron., Tokyo Inst. of Technol., Japan
fYear :
1994
fDate :
5-8 Dec 1994
Firstpage :
151
Lastpage :
156
Abstract :
Methods to derive an efficient memory access pattern for DSPs of which memory is accessed only by address registers (ARs) are discussed. Variables in a program and AR operations are modeled by an access graph. A novel memory allocation method, which removes cycles and forks in a given access graph, and decides an efficient address location of variables in memory space, is proposed. In order to utilize multiple ARs, methods to assign variables into ARs are investigated. The method based on min-cut algorithm is superior to the method based on the simulated annealing technique. The proposed methods are applied to the compiler for DSP56000 and generated codes for several examples are very much improved
Keywords :
digital signal processing chips; graph theory; optimisation; optimising compilers; storage allocation; storage management; DSP compiler; DSP56000; access graph; address registers; code optimization; memory access pattern; memory addressing; memory allocation; min-cut algorithm; simulated annealing; Digital filters; Digital signal processing; Digital signal processors; Flexible printed circuits; Optimization methods; Program processors; Read-write memory; Registers; Signal processing algorithms; Simulated annealing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1994. APCCAS '94., 1994 IEEE Asia-Pacific Conference on
Conference_Location :
Taipei
Print_ISBN :
0-7803-2440-4
Type :
conf
DOI :
10.1109/APCCAS.1994.514540
Filename :
514540
Link To Document :
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