Maple: a simultaneous technology mapping, placement, and global routing algorithm for FPGAs

Author

Togawa, Nozomu ; Sato, Masao ; Ohtsuki, Tatsuo

Author_Institution

Dept. of Electr. Eng., Waseda Univ., Tokyo, Japan

fYear

1994

fDate

5-8 Dec 1994

Firstpage

554

Lastpage

559

Abstract

Technology mapping algorithms for LUT (Look Up Table) based FPGAs have been proposed to transfer a Boolean network into logic-blocks. However, since those algorithms take no layout information into account, they do not always lead to excellent results. In this paper, a simultaneous technology mapping, placement and global routing algorithm for FPGAs, Maple, is presented. Maple is an extended version of a simultaneous placement and global routing algorithm for FPGAs, which is based on recursive partition of layout regions and block sets. Maple inherits its basic process and executes the technology mapping simultaneously in each recursive process. Therefore, the mapping can be done with the placement and global routing information. Experimental results for some benchmark circuits demonstrate its efficiency and effectiveness

Keywords

circuit layout CAD; field programmable gate arrays; integrated circuit layout; logic CAD; network routing; FPGA layout; Maple; global routing algorithm; placement algorithm; recursive partition; technology mapping algorithm; Application specific integrated circuits; Field programmable gate arrays; Random access memory; Routing; Simultaneous localization and mapping; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994. APCCAS '94., 1994 IEEE Asia-Pacific Conference on

Conference_Location

Taipei

Print_ISBN

0-7803-2440-4

Type

conf

DOI

10.1109/APCCAS.1994.514611

Filename

514611