FPGA based dead-time compensation for PWM inverters

Dead-times of power switches causes significant errors in some electric drive applications. Compensation of the error can be done with a small amount of discrete components and small programmable logic circuit. Larger field programmable gate array (FPGA) circuit allows integration of the modulator and compensation logic in the same circuit resulting a very compact and cheap solution. This paper presents one solution to implement a dead-time compensation logic with a cheap and exact voltage feedback and a simple logic that can be implemented in a FPGA or application specific integrated circuits (ASIC). Full test system and measurement results are presented