Title :
Propagation and diagnosis faulty LUTs in an FPGA
Author :
Kumar, T. Nandha
Author_Institution :
Dept. of Electr. & Electron. Eng., Univ. of Nottingham, Semenyih, Malaysia
Abstract :
This paper proposes a new technique for propagation and diagnosis the faulty LUTs (Look Up Tables) in an FPGA (Field Programmable Gate Arrays) using a simple parallel in serial out shift register. The proposed fault propagation design helps in diagnosing the multiple faulty LUTs precisely by avoiding any fault masking. This method has been tested on the commercial FPGA and the experimental results are provided. The experimental result shows that time taken to test 4656 LUTs exhaustively is 196 seconds.
Keywords :
field programmable gate arrays; shift registers; FPGA; fault propagation design; faulty look up tables diagnosis; field programmable gate arrays; parallel in serial out shift register; time 196 s; FPGA testing; Fault diagnosis; Fault propagation; LUT testing; multiple LUT faults;
Conference_Titel :
Electronics Packaging Technology Conference (EPTC), 2010 12th
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-8560-4
Electronic_ISBN :
978-1-4244-8561-1
DOI :
10.1109/EPTC.2010.5702671
