Title :
Irregular NoC simulation framework: IrNIRGAM
Author :
Choudhary, Naveen ; Gaur, M.S. ; Laxmi, V.
Author_Institution :
Dept. of Comput. Sci. & Eng., MPUAT, Udaipur, India
Abstract :
IrNIRGAM is a discrete event cycle accurate simulator written in SystemC and C++ for Network-on-Chip performance simulation. IrNIRGAM supports regular as well as irregular topology framework with source and table based routing. In general, the topology represents the most important characteristic of NoC architectures. It defines how router nodes are physically interconnected and has a predominant influence on network performance and implementation costs. The direct network architecture where each IP Core is directly connected to a dedicated router is assumed for IrNIRGAM. In IrNIRGAM, input buffered routers can have multiple virtual channels (VCs) and uses wormhole switching for flow control. The packets are split into an arbitrary number of flits (flow control units) and forwarded through the network in a pipelined fashion. A Round-Robin scheme for switch arbitration is used in the router nodes to provide fair bandwidth allocation while effectively preventing scheduling anomalies like starvation.
Keywords :
bandwidth allocation; network routing; network-on-chip; C++; IrNIRGAM; SystemC; discrete event cycle accurate simulator; fair bandwidth allocation; flow control units; irregular NoC simulation framework; irregular topology framework; multiple virtual channels; network-on-chip performance simulation; round-robin scheme; router nodes; scheduling anomalies prevention; source based routing; switch arbitration; table based routing; wormhole switching; Clocks; Network topology; Routing; System recovery; Throughput; Tiles; Topology; IP Core; Interconnection Networks; Network-on-Chip; Simulation; System-on-Chip;
Conference_Titel :
Emerging Trends in Networks and Computer Communications (ETNCC), 2011 International Conference on
Conference_Location :
Udaipur
Print_ISBN :
978-1-4577-0239-6
DOI :
10.1109/ETNCC.2011.5958474