Definition of a systematic method for the generation of software test programs allowing the functional verification of system on chip (SoC)

We present a novel approach for hardware functional verification of system on chip (SoC). Our approach is based on the use of on chip programmable processors like CPUs or DSPs to generate test programs for hardware parts of the design. Traditionally test programs are written at a low level using specific functions for hardware accesses. This method is time consuming and error prone as tests are hand written. We introduce a method allowing the use of high level software test programs. The link between hardware and software is achieved by using a custom operating system. We focus on the benefits that are obtained by handling high level test programs.