DocumentCode
2360176
Title
Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices
Author
Nomura, Kumiko ; Abe, Keiko ; Fujita, Shinobu ; DeHon, Andre
Author_Institution
Corporate R&D Center, Toshiba Corp.,, Kawasaki
fYear
2006
fDate
Sept. 2006
Firstpage
1
Lastpage
5
Abstract
The authors present a novel 3D crossbar for future network-on-a-chip implementations. They introduce a routing algorithm for the 3D crossbar circuit and detail two specific 3D crossbar topologies. They evaluate the defect tolerance of the 3D crossbar and quantify the number of extra layers required to support arbitrary permutations as a function of the defect rate. Further, we estimate the circuit performance and advantages of the 3D crossbar circuit based on post-silicon devices
Keywords
fault tolerance; integrated circuit design; network-on-chip; 3D crossbar circuit; defect tolerance; network-on-chip; Bandwidth; CMOS technology; Circuit synthesis; Design optimization; Network-on-a-chip; Routing; Space technology; Switches; Switching circuits; Wire; network-on-a-chip; post-Si device; three-dimensional crossbar;
fLanguage
English
Publisher
ieee
Conference_Titel
Nano-Networks and Workshops, 2006. NanoNet '06. 1st International Conference on
Conference_Location
Lausanne
Print_ISBN
1-4244-0391-X
Type
conf
DOI
10.1109/NANONET.2006.346226
Filename
4152809
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