Title :
In-line defect density targets for new technology from development to manufacturing
Author :
Shamble, Ed ; Ben-Tzur, Mira ; Sharifzadeh, Shahin
Author_Institution :
Cypress Semicond., San Jose, CA, USA
Abstract :
IC manufacturers continuously shrink device dimensions, in order to gain more value from the silicon. Pushing old technologies to the limits is part of the shrinkage path. One of the key questions to be answered is how low must the in-line defect density be at the various stages of development to ensure an economic, robust, and timely transfer to manufacturing. This paper discusses one solution to this question
Keywords :
integrated circuit design; integrated circuit reliability; integrated circuit testing; integrated circuit yield; production testing; semiconductor process modelling; IC manufacture; Si; device dimensions; device shrinkage path; economic technology transfer; in-line defect density; in-line defect density targets; manufacturing technology; robust technology transfer; silicon wafer value; technology development; technology limits; technology manufacturing; Area measurement; Current measurement; Density measurement; Economic forecasting; Inspection; Manufacturing; Research and development; Robustness; Semiconductor device manufacture; Silicon;
Conference_Titel :
Advanced Semiconductor Manufacturing Conference and Workshop, 1998. 1998 IEEE/SEMI
Conference_Location :
Boston, MA
Print_ISBN :
0-7803-4380-8
DOI :
10.1109/ASMC.1998.731548
