Managing annealing pattern effects in 45nm low power CMOS technology

Author

Morin, P. ; Cacho, F. ; Beneyton, R. ; Dumont, B. ; Bidaud, M. ; Joss, E. ; Gallon, C. ; Ranica, R. ; Villaret, A. ; Bianchini, R. ; Devoivre, T. ; Serret, E. ; Binger, R. ; Barla, K. ; Haond, M. ; Colin, A. ; Bono, H. ; Chaton, C.

Author_Institution

STMicroelectronics, Crolles, France

fYear

2009

fDate

14-18 Sept. 2009

Firstpage

288

Lastpage

291

Abstract

We present a study of the pattern effects induced by spike and laser anneals in LP 45 nm CMOS platform. A complete optical and thermal simulation methodology that provides the intra-field temperature mapping has been developed and validated by electrical measurement. This work enables significant improvements, by decreasing the optical dispersion, through an optimized dummification at long and short scale, possibly the use of an absorbent layer, and by reducing the temperature device sensitivity.

Keywords

CMOS integrated circuits; laser beam annealing; low-power electronics; optical dispersion; absorbent layer; annealing pattern effects; electrical measurement; intrafield temperature mapping; laser annealing; low power CMOS technology; optical dispersion; optimized dummification; spike annealing; temperature device sensitivity; thermal simulation; CMOS process; CMOS technology; Energy management; Implants; Optical sensors; Optimized production technology; Power lasers; Rapid thermal annealing; Technology management; Temperature sensors;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Device Research Conference, 2009. ESSDERC '09. Proceedings of the European

Conference_Location

Athens

ISSN

1930-8876

Print_ISBN

978-1-4244-4351-2

Electronic_ISBN

1930-8876

Type

conf

DOI

10.1109/ESSDERC.2009.5331536

Filename

5331536