DocumentCode :
2365534
Title :
An intelligent power device using poly-Si sandwiched wafer bonding technique
Author :
Kobayashi, Ken-ya ; Hamajima, Tomohiro ; Kikuchi, Hiroaki ; Takahashi, Mitsuasa ; Arai, Kenichi
Author_Institution :
Semicond. Div., NEC Corp., Kawasaki, Japan
fYear :
1995
fDate :
23-25 May 1995
Firstpage :
58
Lastpage :
62
Abstract :
A new simple isolation structure has been realized by using poly-Si sandwiched wafer bonding technique. We confirmed that the poly-Si layer enabled the bonded interface to be void-free and electrically perfect, and had the effect that it enabled the reverse recovery time of the parasitic diode of Vertical DMOSFET (VDMOS) to be short. In the new structure, the isolation capabilities were adequate to integrate 60 V VDMOS and control circuits on the same chip. Especially, the parasitic bipolar action has been suppressed. We evaluated an intelligent power device which uses this technique and have confirmed the availability of the new isolation structure
Keywords :
BiCMOS integrated circuits; MOS integrated circuits; isolation technology; power MOSFET; power integrated circuits; silicon; wafer bonding; 60 V; Si; VDMOS devices; control circuits; intelligent power device; isolation structure; poly-Si sandwiched wafer bonding; polysilicon layer; vertical DMOSFET; void-free interface; Circuits; Diodes; Doping; Fabrication; Semiconductor films; Substrates; Surface treatment; Switches; Ultra large scale integration; Wafer bonding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Power Semiconductor Devices and ICs, 1995. ISPSD '95., Proceedings of the 7th International Symposium on
Conference_Location :
Yokohama
ISSN :
1063-6854
Print_ISBN :
0-7803-2618-0
Type :
conf
DOI :
10.1109/ISPSD.1995.515009
Filename :
515009
Link To Document :
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