Title :
CMOS-on-SOI ESD protection networks
Author :
Voldman, S. ; Schulz, R. ; Howard, J. ; Gross, V. ; Wu, S. ; Yapsir, A. ; Sadana, D. ; Hovel, H. ; Walker, J. ; Assaderaghi, E. ; Chen, B. ; Sun, J.Y.-C. ; Shahidi, G.
Author_Institution :
Microelectron. Div., IBM Corp., Essex Junction, VT, USA
Abstract :
ESD robustness of 4 kV HBM is achieved in CMOS-on-SOI ESD protection networks in an advanced sub-0.25 μm CMOS-on-SOI technology. Design layout, body contact, floating gate effects and novel ESD protection implementations are discussed.
Keywords :
CMOS integrated circuits; electrostatic discharge; integrated circuit layout; integrated circuit technology; protection; silicon-on-insulator; 0.25 micron; 4 kV; CMOS-on-SOI technology; ESD protection networks; ESD robustness; Si; body contact effects; design layout; floating gate effects; CMOS integrated circuits; Electrostatic discharges; Integrated circuit fabrication; Integrated circuit layout; Protection; Silicon on insulator technology;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium, 1996. Proceedings
Print_ISBN :
1-878303-69-4
DOI :
10.1109/EOSESD.1996.865156
