Title :
High-performance Si Nanowire FET with a semi gate-around structure suitable for integration
Author :
Sato, Soshi ; Kamimura, Hideyuki ; Arai, Hideaki ; Kakushima, Kuniyuki ; Ahmet, P. ; Ohmori, Kenji ; Yamada, Keisaku ; Iwai, Hisato
Author_Institution :
Frontier Res. Center, Tokyo Inst. of Technol., Yokohama, Japan
Abstract :
Silicon Nanowire (Si NW) FETs with semi gate-around structures suitable for integration were fabricated using conventional planar CMOS processes. With the use of SiO2 pedestal and SiN sidewalls, lithography and etching steps over NW can be easily processed. A large on-current of 49.6 muA at Vg- Vth=1.0 V has been obtained. This value is one of the highest current per nanowire, even though the gate length (200 nm) and gate oxide thickness (5 nm) were relatively large, thanks to high mobility of 387 cm2/Vs. Regarding the off -current control, Ion/Ioff ratio and S.S. were 107 and 71 mV/dec., respectively. We discussed the case of multi-nanowire FET structure based our results. It can be concluded that multi-Si nanowire FET reveals much larger on-current than that of conventional planar FET.
Keywords :
elemental semiconductors; field effect transistors; nanowires; silicon; Si; conventional planar CMOS process; current 49.6 muA; etching steps; lithography steps; multinanowire FET structure; semi gatearound structures; silicon nanowire; voltage 1 V; CMOS process; CMOS technology; Double-gate FETs; Dry etching; Electrodes; Fabrication; Lithography; Oxidation; Shape; Silicon compounds;
Conference_Titel :
Solid State Device Research Conference, 2009. ESSDERC '09. Proceedings of the European
Conference_Location :
Athens
Print_ISBN :
978-1-4244-4351-2
Electronic_ISBN :
1930-8876
DOI :
10.1109/ESSDERC.2009.5331825
