A test generation approach for systems-on-chip that use intellectual property cores

Author

Jiang, Zhigang ; Gupta, Sandeep K.

Author_Institution

Dept. of EE-Syst., Univ. of Southern California, Los Angeles, CA, USA

fYear

2003

fDate

16-19 Nov. 2003

Firstpage

278

Lastpage

281

Abstract

In this paper, we propose a hierarchical automatic test pattern generation (ATPG) framework that can generate custom tests for full-scan systems-on-chip (SOCs) containing intellectual property (IP) cores without revealing much IP. The proposed ATPG is shown to be correct and complete and its average and worst case complexities are shown to be comparable with those of classical ATPG. The proposed ATPG reduces DFT overheads and test application costs. It also enables utilization of a range of test methodologies at the SOC level.

Keywords

automatic test pattern generation; computational complexity; design for testability; fault diagnosis; industrial property; integrated circuit design; integrated circuit testing; logic design; logic testing; system-on-chip; ATPG; DFT overheads; IP cores; SOC level test methodologies; average complexity; custom tests; hierarchical automatic test pattern generation framework; intellectual property cores; systems-on-chip; test application costs; test generation; worst case complexity; Automatic test pattern generation; Automatic testing; Circuit testing; Complexity theory; Control systems; Costs; Design for testability; Fault diagnosis; Integrated circuit design; Integrated circuit testing; Intellectual property; Logic circuit testing; Logic design; Performance evaluation; Protection; System testing; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2003. ATS 2003. 12th Asian

ISSN

1081-7735

Print_ISBN

0-7695-1951-2

Type

conf

DOI

10.1109/ATS.2003.1250823

Filename

1250823