Title :
Active noise cancellation using aggressor-aware clamping circuit for robust on-chip communication
Author :
Katoch, Atul ; Meijer, Maurice ; Jain, Sanjeev K.
Author_Institution :
Philips Res. Labs., Eindhoven, Netherlands
Abstract :
As the IC process technology scales the on-chip wiring network becomes denser. Increasing aspect ratios of the on-chip interconnects lead to higher coupling capacitances and ultimately higher cross-talk noise, which degrades signal integrity. In this paper we propose a clamping circuit for on-chip busses, which clamps a victim wire in an on-chip bus based on the states of its immediate aggressors. These clampers help the driver of the victim wire in draining the charge, which is induced due to cross-talk between aggressors and victim wires. This helps in decreasing the cross-talk peak noise and also the delay variability (referred to as delay noise). Simulation results for a 10 mm long communication bus (parallel wires) laid at minimum pitch in 0.13 μm CMOS technology show that a reduction of 30%(17.6%), 37%(27.2%) and 26%(65.8%) in cross-talk peak noise amplitude (delay noise) is observed for point to point, parallel repeater inserted and staggered repeater inserted respectively when only immediate neighbours are considered (1st order). Furthermore the aggressor-aware clamper is very effective in avoiding glitches, which may occur when more aggressors, in addition to the immediate ones are also switching simultaneously in the same.
Keywords :
CMOS integrated circuits; crosstalk; integrated circuit design; integrated circuit interconnections; integrated circuit noise; system buses; 0.13 micron; CMOS technology; IC process technology; active noise cancellation; aggressor-aware clamping circuit; aspect ratios; communication bus; coupling capacitances; cross-talk noise; delay noise; on-chip bus; on-chip interconnects; robust on-chip communication; CMOS technology; Circuits; Clamps; Crosstalk; Delay; Noise cancellation; Noise level; Noise reduction; Noise robustness; Wire;
Conference_Titel :
VLSI Design, 2005. 18th International Conference on
Print_ISBN :
0-7695-2264-5
DOI :
10.1109/ICVD.2005.42