DocumentCode :
2369206
Title :
A VLSI 128-processor chip for multiresolution image processing
Author :
Albanesi, M.G. ; Cantoni, V. ; Ferretti, M. ; Mainieri, F.
Author_Institution :
Dipartimento di Inf. e Sistemistica, Pavia Univ., Italy
fYear :
1994
fDate :
2-6 May 1994
Firstpage :
296
Lastpage :
307
Abstract :
This paper presents the design of a multiprocessor chip integrating 128 simple processors arranged as a mesh of 8 rows by 16 columns. This mesh of PEs is intermingled with a dual mesh of switching elements, that interconnect the PEs and reconfigure them into one of three topologies. i) an 8-connected standard mesh, ii) a set of 4-connected independent meshes: iii) a quad-tree. This architecture is a viable solution to the problem of embedding into silicon a quad-pyramid, a well known multi-resolution structure for image processing. Local memory is shared between PEs of the same row and the address space increases with the level of the pyramid. The embedding supports fault-tolerance by column substitution
Keywords :
VLSI; image processing; microprocessor chips; multiprocessing systems; special purpose computers; 4-connected independent meshes; 8-connected standard mesh; VLSI; column substitution; embedding; fault-tolerance; multiresolution image processing; quad-pyramid; quad-tree; switching elements; Clocks; Computer vision; Fault tolerance; Image processing; Image resolution; Multiresolution analysis; Silicon; Spatial resolution; Topology; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Massively Parallel Computing Systems, 1994., Proceedings of the First International Conference on
Conference_Location :
Ischia
Print_ISBN :
0-8186-6322-7
Type :
conf
DOI :
10.1109/MPCS.1994.367066
Filename :
367066
Link To Document :
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