A RF circuit design methodology dedicated to critical applications

Author

Cimino, Mikael ; Lapuyade, H. ; de Matos, M. ; Taris, T. ; Deval, Y. ; Bégueret, J.B.

Author_Institution

IMS Lab., Talence

fYear

2007

fDate

2-5 July 2007

Firstpage

53

Lastpage

56

Abstract

This paper presents a reliable design methodology dedicated to radio frequency integrated circuits. This methodology is based on common mask design techniques to avoid CMOS failure and on a cold standby redundancy that permits fault tolerance. The methodology has been applied to a low noise amplifier (LNA) demonstrator dedicated to ZigBee applications. The test chip has been realized in a 0.13 mum CMOS VLSI technology. The LNA provides a measured power gain of 12 clBm and a 3.6 dB noise figure, while consuming only 4 mW under a 1.2 V power supply. Measurements on the test chip demonstrate that the addition of the blocks, which achieve the reliable methodology, have no impact on the LNA performances while being efficient.

Keywords

CMOS integrated circuits; VLSI; fault tolerance; integrated circuit design; integrated circuit reliability; low noise amplifiers; radiofrequency integrated circuits; CMOS VLSI technology; CMOS failure; LNA; RF circuit design; cold standby redundancy; common mask design techniques; fault tolerance; low noise amplifier; radio frequency integrated circuits; CMOS technology; Circuit synthesis; Design methodology; Fault tolerance; Integrated circuit noise; Integrated circuit reliability; Radio frequency; Radiofrequency integrated circuits; Redundancy; Semiconductor device measurement; Built-In Current Sensor; Built-In Self Test; CMOS VLSI; CMOS reliability; RF Low Noise Amplifier; Robustness;

fLanguage

English

Publisher

ieee

Conference_Titel

Research in Microelectronics and Electronics Conference, 2007. PRIME 2007. Ph.D.

Conference_Location

Bordeaux

Print_ISBN

978-1-4244-1000-2

Electronic_ISBN

978-1-4244-1001-9

Type

conf

DOI

10.1109/RME.2007.4401809

Filename

4401809