DocumentCode
236963
Title
Impedance transparency design for PCI-Express Gen 3 SerDes channel on HDI PCBs
Author
Jue Chen ; Sen, Baha
Author_Institution
Cisco Syst., Inc., San Jose, CA, USA
fYear
2014
fDate
4-8 Aug. 2014
Firstpage
631
Lastpage
635
Abstract
AC-coupling capacitor and transition via are the two areas discussed in this paper for the impedance transparency design of a PCI Express Gen 3 backplane channel. The simulation results show that the optimized ground gap for the AC-coupling capacitors and the optimized transition vias helps improve the channel impedance transparency.
Keywords
capacitors; peripheral interfaces; printed circuits; AC-coupling capacitor; HDI PCBs; PCI-Express Gen 3 SerDes backplane channel; channel impedance transparency design; optimized ground gap; optimized transition; Backplanes; Capacitors; Electromagnetic compatibility; Impedance; Optimization; Solid modeling; Three-dimensional displays; AC-coupling capacitor; PCI Express; impedance; transition via;
fLanguage
English
Publisher
ieee
Conference_Titel
Electromagnetic Compatibility (EMC), 2014 IEEE International Symposium on
Conference_Location
Raleigh, NC
Print_ISBN
978-1-4799-5544-2
Type
conf
DOI
10.1109/ISEMC.2014.6899047
Filename
6899047
Link To Document