Revisiting VLSI interconnects in deep sub-micron: some open questions

Author

Dasgupta, Parthasarathi

Author_Institution

Indian Inst. of Manage. Calcutta, Kolkata, India

fYear

2005

fDate

3-7 Jan. 2005

Firstpage

615

Lastpage

620

Abstract

Deep sub-micron technology has increased the design complexity of VLSI circuits. Design of routers now has to take care of the timing issues for faster design convergence. This has yielded wider scope of research in design and performance of interconnects. We focus on certain critical aspects of interconnects, and related open research issues. The discussions are on (i) the fidelity of delay estimators, and its use in finding global routing trees, (ii) a new class of routing trees, and (in) the evolution of new metric for interconnect performance measurement.

Keywords

CMOS integrated circuits; VLSI; circuit complexity; delay estimation; integrated circuit design; integrated circuit interconnections; integrated circuit measurement; network routing; VLSI circuits; VLSI interconnects; deep submicron technology; delay estimators; design complexity; design convergence; global routing trees; interconnect performance measurement; routers design; CMOS technology; Delay estimation; Delay lines; Integrated circuit interconnections; Measurement; Routing; Technology management; Timing; Very large scale integration; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2005. 18th International Conference on

ISSN

1063-9667

Print_ISBN

0-7695-2264-5

Type

conf

DOI

10.1109/ICVD.2005.149

Filename

1383342