DocumentCode :
2370893
Title :
High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme
Author :
Wu, C.C. ; Lin, D.W. ; Keshavarzi, A. ; Huang, C.H. ; Chan, C.T. ; Tseng, C.H. ; Chen, C.L. ; Hsieh, C.Y. ; Wong, K.Y. ; Cheng, M.L. ; Li, T.H. ; Lin, Y.C. ; Yang, L.Y. ; Lin, C.P. ; Hou, C.S. ; Lin, H.C. ; Yang, J.L. ; Yu, K.F. ; Chen, M.J. ; Hsieh, T.H.
Author_Institution :
R&D, Taiwan Semicond. Manuf. Co., Hsinchu, Taiwan
fYear :
2010
fDate :
6-8 Dec. 2010
Abstract :
A high performance 22/20nm CMOS bulk FinFET achieves the best in-class N/P Ion values of 1200/1100 μA/μm for Ioff=100nA/μm at 1V. Excellent device electrostatic control is demonstrated for gate length (Lgate) down to 20nm. Dual-Epitaxy and multiple stressors are essential to boost the device performance. Dual workfunction (WF) with an advanced High-K/Metal gate (HK/MG) stack is deployed in an integration-friendly CMOS process flow. This dual-WF approach provides excellent Vth roll-off immunity in the short-channel regime that allows properly positioning the long-channel device Vth. Enhanced 193nm immersion lithography has enabled the stringent requirements of the 22/20nm ground rules. Reliability of our advanced HK/MG stack is promising. Excellent SRAM static noise margin at 0.45V is reported.
Keywords :
CMOS integrated circuits; MOSFET; electrostatics; immersion lithography; FinFET CMOS device; SRAM static noise margin; device electrostatic control; dual workfunction; dual-WF approach; dual-epitaxy; high-K/metal gate scheme; immersion lithography; multiple stressor; wavelength 193 nm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting (IEDM), 2010 IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0163-1918
Print_ISBN :
978-1-4424-7418-5
Electronic_ISBN :
0163-1918
Type :
conf
DOI :
10.1109/IEDM.2010.5703430
Filename :
5703430
Link To Document :
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