Title :
Two techniques for minimizing power dissipation in scan circuits during test application
Author :
Chakravarty, Sreejit ; Dabholkar, Vinay P.
Author_Institution :
Dept. of Comput. Sci., State Univ. of New York, Buffalo, NY, USA
Abstract :
Two techniques for reducing power dissipation during test application, when scan test structure is used, are proposed. Problems required to exploit these techniques are defined. They are shown to be intractable. Heuristics required to exploit the proposed techniques are discussed. Experimental results are presented
Keywords :
CMOS logic circuits; VLSI; logic testing; CMOS; VLSI; full integrated scan; heuristics; model; power dissipation minimisation; scan circuits; test application; Application software; Batteries; Circuit testing; Partial discharges; Power dissipation; Power supplies; Semiconductor device modeling; Switching circuits; System testing; Very large scale integration;
Conference_Titel :
Test Symposium, 1994., Proceedings of the Third Asian
Conference_Location :
Nara
Print_ISBN :
0-8186-6690-0
DOI :
10.1109/ATS.1994.367211
