Title :
On crosstalk fault detection in hierarchical VLSI logic circuits
Author :
Liaud, A. ; Fourniols, J.-Y. ; Sicard, E.
Author_Institution :
Inst. Nat. des Sci. Appliquees, Toulouse, France
Abstract :
A realistic crosstalk fault detector operating at hierarchical layout and logic level is presented. A set of filtering schemes are proposed to reduce considerably the set of probable single and multiple coupling faults with details on substrate resistivity and unbalanced buffer implications. Comparisons between flat and hierarchical layout approaches are reported together with the performances of the tool for various IC implementations
Keywords :
VLSI; crosstalk; fault diagnosis; integrated circuit noise; integrated circuit testing; integrated logic circuits; logic testing; crosstalk fault detection; double coupling crosstalk; filtering schemes; hierarchical VLSI logic circuits; multiple coupling faults; scaling down; single coupling faults; substrate resistivity; unbalanced buffer implications; CMOS technology; Capacitance; Circuit faults; Circuit testing; Crosstalk; Electrical fault detection; Integrated circuit modeling; Logic circuits; Very large scale integration; Voltage;
Conference_Titel :
Test Symposium, 1994., Proceedings of the Third Asian
Conference_Location :
Nara
Print_ISBN :
0-8186-6690-0
DOI :
10.1109/ATS.1994.367234
