DocumentCode
2371785
Title
Random test input generation for supply current testing of TTL combinational circuits
Author
Hashizume, Masaki ; Tsukimoto, Isao ; Tamesada, Takemomi
Author_Institution
Fac. of Eng., Tokushima Univ., Japan
fYear
1994
fDate
15-17 Nov 1994
Firstpage
132
Lastpage
137
Abstract
In this paper, a random test generation algorithm for supply current testing of TTL combinational circuits is proposed. In this method, by inserting equivalent faults first in the direction from the primary output ports to the primary input ports, the total number of fault simulations can be decreased. In this paper it is shown that test input vector can be derived more quickly by means of the algorithm
Keywords
automatic testing; combinational circuits; electric current measurement; fault diagnosis; fault location; logic testing; random processes; transistor-transistor logic; TTL combinational circuits; equivalent faults; fault simulation; primary input ports; primary output ports; random test input generation; supply current testing; test input vector; Circuit faults; Circuit testing; Combinational circuits; Current supplies; Electrical fault detection; Fault detection; Logic circuits; Logic testing; Random number generation; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 1994., Proceedings of the Third Asian
Conference_Location
Nara
Print_ISBN
0-8186-6690-0
Type
conf
DOI
10.1109/ATS.1994.367241
Filename
367241
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