Insight Into a Generic Interconnect Resource Model for Xilinx Virtex and Spartan Series FPGAs

With increasing scale of field-programmable gate arrays (FPGAs), the architecture of interconnect resources (IRs) in FPGAs is becoming more and more complicated. FPGAs become more vulnerable to defects during manufacturing or lifetime operation. IR testing plays an important role to guarantee correct functionality of FPGAs. This brief provides insight into a generic IR model that we developed. This IR model is a directed and weighted graph and can exhibit connection relationships among wire segments in FPGAs. Based on the generic IR model, a routing algorithm to automatically derive the minimal or near-minimal set of test configurations for IRs of Virtex and Spartan series FPGAs is also proposed. The generic IR model and associated routing algorithm are verified in Virtex, Virtex-II, Virtex-4, Virtex-5, Virtex-6, 7 Series, and Spartan series FPGAs, respectively. The experimental results demonstrate that the proposed IR model with the accompanying routing algorithm is applicable to these FPGAs with IR full coverage achieved.