A quantitative inquisition into ESD sensitivity to strain in nanoscale CMOS protection devices

This paper presents the first detailed experimental investigation together with theoretical analysis of the impact of strain on ESD robustness in nanometer scale planar CMOS protection devices in both bulk and SOI technologies. Gated diodes as well as NMOS devices in both gate-grounded (GG) and gate-tied-high (GH) configurations are investigated. It is shown that the ESD sensitivity to strain can vary substantially depending on whether the stressed devices are bulk or SOI, and on the mode in which they are stressed. Modulation of snapback region due to strain and its impact on device electrical stability, competing requirements for ballasting and strain effects, strain non-uniformity induced performance reduction, as well as comparative analysis of ESD vs DC performance improvement are discussed in detail. Increase in ESD robustness of about 20% is obtained for bulk gated-diodes and SOI GG-NMOS, due to strain engineering. On the other hand, it is shown that high tensile strain can influence the bipolar action of bulk GG-NMOS by enhancing the snapback behavior. Insights are provided in this work to specify guidelines in terms of device configuration, operation principle and type of strain in order to leverage maximum improvement from strain engineering.