Bounding error masking in linear output space compression schemes

Author

Tarnick, Steffen

Author_Institution

Fault-Tolerant Comput. Group, Potsdam Univ., Germany

fYear

1994

fDate

15-17 Nov 1994

Firstpage

27

Lastpage

32

Abstract

Based on the principle of linear output space compression we present a design method for concurrent checkers such that the masking probability of errors caused by faults of a given set of circuit faults is below a given bound, while keeping the space compression ratio, defined as the ratio of the number of circuit outputs to the number of outputs of the space compressor, as high as possible. Experiments performed on the ISCAS-85 benchmark circuits show that the compression ratios achieved with compression functions computed with this method can be very high, even for very low bounds for the error masking probability and large fault sets

Keywords

error detection; fault location; logic design; logic testing; probability; ISCAS-85 benchmark circuits; bounding error masking; circuit faults; compression ratios; concurrent checkers; error masking probability; linear output space compression; space compression ratio; Boolean functions; Built-in self-test; Circuit faults; Concurrent computing; Design methodology; Electrical fault detection; Fault detection; Fault tolerance; Linear code;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1994., Proceedings of the Third Asian

Conference_Location

Nara

Print_ISBN

0-8186-6690-0

Type

conf

DOI

10.1109/ATS.1994.367258

Filename

367258