• DocumentCode
    2372187
  • Title

    A 0.8W HDTV video processor with simultaneous decoding of two MPEG2 MP@HL streams and capable of 30frames/s reverse playback

  • Author

    Yamauchi, Hiroyuki ; Okada, Shogo ; Taketa, Koji ; Yuh Matsuda ; Mori, Takayoshi ; Okada, Shogo ; Watanabe, Toshio ; Harada, Y. ; Matsudaira, M. ; Matsushita, Yuki

  • Author_Institution
    Sanyo Electric Co., Ltd.
  • Volume
    2
  • fYear
    2002
  • fDate
    7-7 Feb. 2002
  • Firstpage
    300
  • Lastpage
    514
  • Keywords
    Decoding; Frequency conversion; HDTV; Hardware; High definition video; Pipelines; SDRAM; Size control; Streaming media; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • Print_ISBN
    0-7803-7335-9
  • Type

    conf

  • DOI
    10.1109/ISSCC.2002.992264
  • Filename
    992264
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2372187