DocumentCode
2372192
Title
Performance analysis of multiple bus interconnection networks with hierarchical requesting model
Author
Sheu, Jang-Ping ; Chen, Wen-Tsuen
Author_Institution
Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
fYear
1988
fDate
13-17 Jun 1988
Firstpage
138
Lastpage
144
Abstract
The performance of multiple-bus networks with full bus-memory connection, single bus-memory connection, and partial bus-memory connection are presented. A type of multiple-bus network, called a partial bus network with K classes, is proposed. Under a nonuniform requesting model called a hierarchical requesting model, the performance of the above multiple-bus networks is analyzed. The costs and fault-tolerant capabilities of each are evaluated and compared with one another. It is shown that the proposed networks are useful in applications requiring high performance and degree of fault tolerance with moderate cost
Keywords
multiprocessor interconnection networks; performance evaluation; fault-tolerant capabilities; hierarchical requesting model; multiple bus interconnection networks; nonuniform requesting model; partial bus network; performance model; Bandwidth; Computer architecture; Costs; Fault tolerance; Joining processes; Multiprocessing systems; Multiprocessor interconnection networks; Performance analysis; Throughput; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Distributed Computing Systems, 1988., 8th International Conference on
Conference_Location
San Jose, CA
Print_ISBN
0-8186-0865-X
Type
conf
DOI
10.1109/DCS.1988.12511
Filename
12511
Link To Document