FPGA reconfigurability in the presence of logic and I/O faults

The SRAM FPGA´s reconfigurability is investigated with a view to addressing the problems of reparability through the utilization of a device´s unused logic and routing resources. This is done by remapping the design such that the faulty logic is bypassed. This paper addresses the issue of mapping designs onto FPGAs with single and multiple logic and I/O block faults subject to the constraint that the faults are correctly identified, localized, and excluded from the pool of available logic and I/O cells. The viability of the proposed approach depends on the maintenance, within acceptable performance parameters, of the reconfigured circuit´s throughput and interface characteristics. The reconfigurability of representative complex butterfly circuit in the presence of single and multiple faults is considered and relevant simulation results based on the ORCA 2C40 device are presented