Timing and Carrier Acquisition in Upstream CATV Channels

This paper provides synchronization circuits to be used in the upstream receiver of a CATV network. These circuits, which are structured for implementation in an FPGA, are for detecting the beginning of a burst, recovering timing and determining the carrier frequency offset. These circuits comply with the North American standard ANSI/SCTE. Timing and carrier frequency acquisition occur simultaneously. It is found that the timing recovery circuit is quite insensitive to carrier frequency offsets as large as 30 degrees per symbol. The standard deviation on the timing error is less than 1.3% of a symbol for E_bN₀ greater than 20 dB. The standard deviation on the frequency error is less than 0.6 degrees per symbol for E_b/N₀ greater than 20 dB