• DocumentCode
    2375693
  • Title

    A dual-band 61.4∼63GHz/75.5∼77.5GHz CMOS receiver in a 90nm technology

  • Author

    Chen, Ke-Hou ; Lee, Chihun ; Liu, Shen-Iuan

  • Author_Institution
    Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
  • fYear
    2008
  • fDate
    18-20 June 2008
  • Firstpage
    160
  • Lastpage
    161
  • Abstract
    A dual-band 61.4~63 GHz/75.5~77.5 GHz receiver has been realized in a 90 nm CMOS technology. It is composed of a broadband low-noise amplifier, RF/IF mixers, and a quadruplicate-locked phase-locked loop. With the dual down-conversion approach, this dual-band receiver achieves a conversion voltage gain of 25.2 dB at 62.5 GHz and 19.4 dB at 77 GHz with an input P1dB of -16 dBm. It consumes 132 mW from a 1.5 V supply.
  • Keywords
    CMOS integrated circuits; intermediate-frequency amplifiers; low noise amplifiers; mixers (circuits); phase locked loops; radiofrequency amplifiers; receivers; wideband amplifiers; CMOS receiver; IF mixers; RF mixers; broadband amplifier; frequency 61.4 GHz to 63 GHz; frequency 75.5 GHz to 77.5 GHz; gain 19.4 dB; gain 25.2 dB; low-noise amplifier; power 132 mW; quadruplicate-locked phase-locked loop; size 90 nm; voltage 1.5 V; Bandwidth; CMOS technology; Circuit simulation; Dual band; Microstrip; Noise measurement; Phase locked loops; Radio frequency; Switches; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2008 IEEE Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4244-1804-6
  • Electronic_ISBN
    978-1-4244-1805-3
  • Type

    conf

  • DOI
    10.1109/VLSIC.2008.4585990
  • Filename
    4585990
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2375693