Development of a tapeless lead-on-chip (LOC) package

Author

Amagai, Masazumi ; Baumann, Robert ; Kamei, Shigenori ; Ohsumi, Masaki ; Kawasaki, Eiji ; Kitagawa, Hideki

Author_Institution

ULSI Technol. Dev., Texas Instrum. Japan Ltd., Ibaraki, Japan

fYear

1994

fDate

1-4 May 1994

Firstpage

506

Lastpage

512

Abstract

A double-sided adhesive tape is typically used as an insulator and mechanical buffer layer between the chip and lead frame in lead-on-chip (LOC) packages. The costs associated with the lead frame and tape process make the current LOC package ten times more expensive than conventional packaging. A new tapeless LOC package process has been developed which significantly reduces the production costs. In this new process, the tape is replaced by a thermoplastic adhesive layer deposited on the polyimide coated wafer. This paper describes the optimum thermoplastic material properties for the adhesive layer, the fabrication process parameters, and the experimental and simulated reliability and performance results of the tapeless LOC package

Keywords

adhesion; lead bonding; plastic packaging; polymer films; fabrication; insulator; mechanical buffer layer; polyimide coated wafer; production costs; reliability; tapeless LOC package; tapeless lead-on-chip package; thermoplastic adhesive layer; Buffer layers; Costs; Fabrication; Insulation; Lab-on-a-chip; Material properties; Materials reliability; Packaging; Polyimides; Production;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 1994. Proceedings., 44th

Conference_Location

Washington, DC

Print_ISBN

0-7803-0914-6

Type

conf

DOI

10.1109/ECTC.1994.367546

Filename

367546