Dual Mode Logic Carry Look ahead Adder

Carry Look-ahead Adder (CLA) is implemented by using Dual Mode Logic (DML) topologies. DML logic switches between the static and dynamic mode of operations. In dynamic mode achieves higher performance with increase in power consumption and in static mode, DML logic achieves low power dissipation albeit with reduced performance. This feature allowed implementing CLA by selection of carry path based on input vectors. A 4-bit CLA was designed in 45nm TSMC technology using Cadence Virtuoso Design. Simulation results showed gain in speed albeit with increase in power and area when compared to the conventional CMOS logic.